This invention relates generally to timing or clocking circuitry for use with integrated circuits and more particularly, it relates to an integrated circuit which includes an input clock generator circuit responsive to an external TTL level clock signal for generating an internal CMOS level system clock signal and an internal clock generator circuit responsive to either the internal CMOS level system clock signal or an external CMOS level system clock signal for generating internal CMOS phase clock signals.
There are several families of logic circuits which are available for use in implementing the various types of logic functions required in the operation of high speed microprocessors and other digital systems. For example, in conventional transistor-transistor-logic (TTL) the logic values corresponding to binary "1" and "0" are ordinarily represented by a high level voltage greater than 2.0 volts and a low level voltage less than 0.8 volts. On the other hand, complementary metal-oxide-semiconductor (CMOS) logic circuits have a larger voltage swing of 5 volts to 0 volts for the respective binary "1" and "0" states. Thus, these voltage levels are incompatible and an interface or buffer circuit is needed to perform the required voltage level translation. Further, since these various types of logic circuits are used many times in the timing and control of the different signals in the operation of the microprocessor, such various logic circuits require also their own clock signals. As a result, the different clock signals, such as the TTL level clock signals for the TTL logic circuitry and the CMOS level clock signals for the CMOS logic circuitry, are likewise incompatible.
Therefore, it is also generally required to provide interface circuits between the TTL level clock signals and the CMOS level clock signals in order to obtain the required compatibility therebetween. However, this process suffers from the disadvantage of increasing of the propagation delay each time a conversion is needed, effecting the integrated circuit performance in such areas as output signal delay and input data "hold time" when measured relative to the system clock. Another problem encountered with the TTL level clock signals is that they tend to become skewed, i.e., the duty cycle of the clock pulses are different from the 50% on-time and 50% off-time, thereby affecting its performance of operation.
It would therefore be desirable to provide an integrated circuit which includes an input clock generator circuit responsive to an external TTL level clock signal for generating an internal CMOS level system clock signal for its own use and for use by other integrated circuits and an internal clock generator circuit responsive to either the internal CMOS level system clock signal or an external CMOS level system clock signal for generating internal CMOS phase clock signals for its own use. As a result, there is achieved a higher speed of operation and the propagation delay between the external and internal clock signals has been minimized.